This relates to resistor circuitry, and more particularly, to resistor circuitry suitable for use in high speed analog circuit designs.
Analog circuits on an integrated circuit device typically include amplifiers that are used for amplifying alternating current (AC) signals (also referred to as “small” signals). These amplifiers often contain input transistors that are connected to associated loading resistors (i.e., output load resistors). The amplifiers provide a small signal gain that is proportional to the value of the associated loading resistors.
For example, consider a scenario in which a first amplifier contains a first input transistor and a first load resistor connected in series and in which a second amplifier contains a second input transistor and a second load resistor connected in series. The first load resistor may exhibit a first resistance value, whereas the second load resistor may exhibit a second resistance value that is greater than the first resistance value. Assuming that the first and second input transistors have identical transistor characteristics (i.e., same channel type and transistor dimensions) and that the current flowing through the first input transistor is equal to the current flowing through the second input transistor, the second amplifier will exhibit a gain that is greater than that of the first amplifier because the second resistance value is greater than the first resistance value.
An amplifier load resistor is typically connected to the output of an amplifier. Conventional load resistors may exhibit parasitic capacitance that can hinder the performance of the amplifier. If the parasitic capacitance associated with the load resistor is unacceptably large, the rate at which the small signals oscillate at the output of the amplifier may be severely reduced. In order to compensate for this reduction in speed, a greater amount of current may be required to flow through the input transistors. In other words, higher parasitic capacitance undesirably results in reduced performance and/or increased power consumption.
A first type of conventional load resistor includes a polysilicon structure disposed over a shallow trench isolation (STI) structure that is formed in a semiconductor substrate. A gate oxide is interposed between the polysilicon structure and the surface of the substrate where the STI structure is formed. An n-well is formed below the STI structure. A deep n-well is formed below the n-well. The deep n-well is actively driven to a fixed biased voltage. A depletion region is formed at the junction where the STI structure and the n-well meet. A conventional load resistor of this type exhibits a parasitic capacitance value that is proportional to the sum of the oxide thickness, the depth of the STI structure, and the depth of the depletion region within the n-well.
In contrast to the conventional resistor of the first type, a second type of conventional load resistor includes a p-well formed below the STI structure. A deep p-well is formed below the p-well and is actively driven to a fixed biased voltage. A depletion region is formed at the junction where the STI structure and the p-well meet. A load resistor of this type exhibits a parasitic capacitance value that is proportional to the sum of the oxide thickness, the depth of the STI structure, and the depth of the depletion region within the p-well.
The first and second types of conventional load resistors may exhibit unacceptably large parasitic capacitance values unsuitable for use in high speed analog circuit designs. In an effort to develop resistors with reduced parasitic capacitance, a third type of load resistor has been developed in which the STI structure is formed in a native (with dopant concentration levels that are less than 1016 atoms/cm3) semiconductor substrate. The STI structure is formed in neither an n-well nor a p-well. The parasitic capacitance associated with such type of load resistor is substantially lower than that associated with the first and second types of conventional resistors. Integrated circuits that include the third type of load resistors, however, may be unacceptably susceptible to noise, because the substrate is not actively tied to any bias level and may therefore vary sporadically during normal device operation.